1. Field of the Invention
The present invention is related to a method of fabricating semiconductor chips by dicing a semiconductor wafer at a predetermined size.
2. Description of the Related Art
In a conventional semiconductor chip fabrication process, a semiconductor wafer, on which a plurality of semiconductor elements are formed, is diced in a dicing process of the fabrication process by shifting a rotationally-driven disk-shaped cutter (dicing blade) of a semiconductor chip fabrication apparatus vertically and horizontally so as to form a large number of semiconductor chips. In general, such semiconductor chips are box-shaped.
In the above-mentioned conventional semiconductor chip fabrication process, since a dicing blade of a semiconductor chip fabrication apparatus is shifted vertically and horizontally to dice a semiconductor wafer, the semiconductor chip fabrication apparatus has to perform a greater number of cutting operations as more semiconductor chips are formed from the semiconductor wafer. Thus, it takes more dicing time to produce more semiconductor chips.
In addition, when a dicing blade is used in the dicing process, it is necessary to prepare a passage area (dicing line width) for the dicing blade between adjacent semiconductor chips in a semiconductor wafer. In general, an interval between adjacent semiconductor chips has to be set as more than the dicing line width of about 50 μm, and this requirement adversely influences high-density semiconductor chip formation on a semiconductor wafer. Furthermore, a semiconductor wafer has been recently made thinner down to about 50 μm. Such a thin semiconductor wafer is fragile to a dicing blade.
In addition, when a semiconductor wafer is diced to form semiconductor chips, the diced semiconductor chips are box-shaped. Such a box-shaped semiconductor chip has a significant problem in that a corner and an edge of the semiconductor chip may be chipped when the semiconductor chip is handled or carried, resulting in yield reduction thereof.